1 S3014 sonet/sdh clock recovery and synthesis unit bicmos pecl clock generator device specification sonet/sdh clock recovery and synthesis unit S3014 ? features ? complies with ansi, bellcore, and ccitt specifications for jitter tolerance ? on-chip high frequency pll with internal loop filter for clock generation or clock recovery ? supports clock generation for sts-3/stm-1 (155.52 mhz) ? supports clock recovery for sts-3/stm-1 (155.52 mbit/s) or sts-12/stm-4 (622.08 mbit/s) nrz data ? selectable 19.44 mhz, 51.84 mhz, or 155.52 mhz reference frequency ? lock detectmonitors transition density and run length ? low power ? low-jitter ecl interface ? small 44 plcc or clcc package ? ttl reference clock output general description the function of the S3014 clock synthesis and recov- ery unit is to derive high speed timing signals for sonet/sdh-based equipment. the S3014 is imple- mented using amccs proven phase locked loop (pll) technology. in clock recovery mode, the S3014 receives either an sts-3/stm-1 or sts-12/stm-4 scrambled nrz signal and recovers the clock from the data. the chip outputs a differential ecl bit clock and retimed data. in clock synthesis mode, the S3014 receives a 19.44, 51.84, or 155.52 mhz reference clock and out- puts an sts-3/stm-1 or sts-12/stm-4 differential ecl clock. the S3014 utilizes an on-chip pll which consists of a phase detector, a loop filter, and a voltage con- trolled oscillator (vco). the phase detector compares the phase relationship between the vco output and the refclk input, a loop filter converts the phase detector output into a smooth dc voltage, and the dc voltage is input to the vco whose fre- quency is varied by this voltage. a block diagram is shown in figure 1. figure 1. system block diagram 2 3 2 2 2 refckout serclkop/n lockdet serdatop/n refckinp/n tstclken sel(2:0) rst serdatip/n loop filter vco clock divider phase detector lock detector cap1 cap2 los
2 S3014 sonet/sdh clock recovery and synthesis unit S3014 overview clock recovery mode in the clock recovery mode, the S3014 supports clock recovery for the sts-3/stm-1 and sts-12/ stm-4 rates. in this mode, ecl differential serial data is input to the chip at the rate specified by the three sel pins, and clock recovery is performed on the incoming data stream. an external ecl differential reference clock (19.44, 51.84, or 155.52 mhz) is required to minimize the pll lock time and provide a stable output clock source in the absence of serial input data. retimed data and clock are output from the S3014. clock synthesis mode in the clock synthesis mode, the S3014 synthesizes up to the sts-3/stm-1 and sts-12/stm-4 clock rates from either a 19.44 mhz, 51.84 mhz, or 155.52 mhz input reference frequency. sts-3/stm-1 jitter genera tion is compliant with the sonet/sdh requirement for 0.01 u.i. (rms) maximum, given 14.1 ps (rms) jitter on refclk in the 12 khz to 1 mhz frequency band. in this mode, a crystal oscillator is connected to the ecl differential reference input and synthesized up to the output frequency selected using the three sel pins. the clock synthesis mode is recognized by the absence of data on the serdatip/n input pins. in this mode, tie the serdatip pin to ground and tie the serdatin pin to vtt (-2.0v) or to an ecl low level. a programmable internal divider outputs a ttl clock at the same frequency as the reference clock input via the refckout output. the lock detect output will remain consistently low in the clock synthesis mode. characteristics performance the S3014 pll complies with the minimum jitter toler- ance for clock recovery proposed for sonet/sdh equipment defined by the t1x1.6/91-022 document, when used with differential inputs and outputs as shown in figure 2. input jitter tolerance input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input sig- nal that causes an equivalent 1 db optical/electrical power penalty. sonet input jitter tolerance require- ments are shown in figure 2. the measurement condition is the input jitter amplitude which causes an equivalent of 1 db power penalty. jitter generation jitter generation is defined as the amount of jitter at the oc-n/sts-n output of a sonet equipment. jitter generation shall not exceed 0.01 ui rms in oc-3 mode and 0.03 ui rms in oc-12 mode when mea sured using a highpass filter with a 12 khz cutoff frequency. serial data output set-up and hold time the output set-up and hold times are represented by the waveforms shown in figure 3. reference clock input the required characteristics of the reference clock are outlined below. unless otherwise noted, specifi- cations refer to both clock recovery and clock synthesis modes of operation. while a single-ended ecl reference clock may be used, additional jitter due to edge movement related to threshold variations from dc offsets may be induced. figure 2. input jitter tolerance specification f0 f1 f2 f3 ft 0.15 1.5 15 sinusoidal input jitter amplitude (ui p-p) frequency oc/sts level f0 (hz) f2 (hz) f3 (khz) ft (khz) f1 (hz) 3 12 10 10 30 30 300 300 6.5 25 75 250 figure 3. clock output to data transition delay output frequency 155.52 mhz 622.08 mhz serdatop/n setup time 2.5 ns 450 ps serdatop/n hold time 2.5 ns 650 ps t su t h serclkop/n serdatop/n
3 S3014 sonet/sdh clock recovery and synthesis unit pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p n i k c f e r n n i k c f e r . f f i d l c e i1 4 3 4 t i b l a n r e t n i e h t r o f e c n e r e f e r e h t s a d e s u t u p n i . k c o l c e c n e r e f e r e h t n i k c o l c y b d n a t s s a d e s u . e d o m s i s e h t n y s y c n e u q e r f n i k c o l c . e d o m y r e v o c e r k c o l c n i t e s e r g n i r u d r o a t a d f o e c n e s b a p i t a d r e s n i t a d r e s . f f i d l c e i4 6 y r e v o c e r k c o l c e h t n i d e s u s i 4 1 0 3 s e h t n e h w . n i a t a d l a i r e s . s t u p n i e s e h t n o s n o i t i s n a r t e h t m o r f d e r e v o c e r s i k c o l c , e d o m n e k l c t s tl t ti6 3o t t s e t n o i t c u d o r p g n i r u d d e s u . h g i h e v i t c a , e l b a n e k c o l c t s e t . n o i t a r e p o l a m r o n r o f d n u o r g o t e i t . l l p e h t n i o c v e h t s s a p y b 2 l e s 1 l e s 0 l e s l t ti6 2 4 2 3 2 r e f e r . s e i c n e u q e r f t u p n i d n a t u p t u o t c e l e s o t d e s u , t c e l e s e d o m . n o i t a n a l p x e r o f 1 e l b a t o t t s rl t ti3 3d n a e t a t s n w o n k a o t e c i v e d e h t s e z i l a i t i n i . w o l e v i t c a , t e s e r d l e h n e h w , t s r . k c o l c e c n e r e f e r e h t o t e r i u q c a o t l l p e h t s e c r o f e h t o t s t u p t u o t e d k c o l d n a t u o k c f e r e h t s e c r o f o s l a , w o l - r e w o p t a d e i l p p a e b d l u o h s s m 6 1 t s a e l t a f o t e s e r a . e t a t s z - i h e c n e r e f e r e h t o t e r i u q c a e r o t y r a s s e c e n s i t i r e v e n e h w d n a p u e h t f i k c o l c e c n e r e f e r e h t o t e r i u q c a e r o s l a l l i w 4 1 0 3 s e h t . k c o l c ) s o r e z t n a t s n o c r o s e n o t n a t s n o c ( t n e c s e i u q d l e h s i a t a d l a i r e s . s m 6 1 t s a e l t a r o f s o ll c ei2 3e b o t t u p n i l c e k 0 1 d e d n e - e l g n i s a . w o l e v i t c a , l a n g i s f o s s o l s s o l a e t a c i d n i o t e l u d o m r e v i e c e r l a c i t p o l a n r e t x e e h t y b n e v i r d e h t n o a t a d e h t , w o l s i s o l n e h w . r e w o p l a c i t p o d e v i e c e r f o a o t d e c r o f y l l a n r e t n i e b l l i w s n i p ) n / p i t a d r e s ( n i a t a d l a i r e s k c o l o t d e c r o f l l p e h t d n a , w o l d e c r o f t e d k c o l , o r e z t n a t s n o c e r u s s a o t d e s u e b t s u m l a n g i s s i h t . s t u p n i n / p n i k c f e r e h t o t n a g n i w o l l o f a t a d l a i r e s o t n o i t i s i u q c a e r c i t a m o t u a t c e r r o c . h t a p l a c i t p o e h t f o n o i t c e n n o c e r t n e u q e s b u s d n a n o i t p u r r e t n i f o t u o " r e d n a w " t o n s e o d l l p e h t t a h t e r u s s a l l i w s i h t y c n e u q e r f / e s a h p m o d n a r e h t g n i k c a r t y b e g n a r n o i t i s i u q c a e r g n i r o t i n o m e l i h w r o o l f e s i o n s ' r o t c e t e d l a c i t p o e h t f o t n e t n o c s n i p n / p i t a d r e s e h t n o a t a d , h g i h s i s o l n e h w . r e b i f " k r a d " . y l l a m r o n d e s s e c o r p e b l l i w 2 p a c , 1 p a cCi9 3 0 4 r o t i c a p a c e h t . s n i p e s e h t o t d e t c e n n o c , r o t i c a p a c r e t l i f p o o l c i m a r e c c i r t c e l e i d r 7 x , e c n a r e l o t % 0 1 f 1 . 0 e b d l u o h s e u l a v . d e d n e m m o c e r s i v 0 5 . r o t i c a p a c p i h c t e d k c o ll t to 1 1n e h w h g i h t e s . r o t a c i d n i y r e v o c e r k c o l c . h g i h e v i t c a , t c e t e d k c o l g n i m o c n i e h t o t n o d e k c o l s a h y r e v o c e r k c o l c l a n r e t n i e h t t u p t u o s i h t . t u p t u o s u o n o r h c n y s a n a s i t e d k c o l . m a e r t s a t a d n i ; t u p n i a t a d l a i r e s g n i m o c n i o n s i e r e h t n e h w d e t r e s s a e d s i . k c o l c e c n e r e f e r e h t o t s k c o l l l p e h t e s a c h c i h w
4 S3014 sonet/sdh clock recovery and synthesis unit pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p o t a d r e s n o t a d r e s . f f i d l c e o0 2 1 2 s i l a n g i s s i h t , e d o m y r e v o c e r k c o l c e h t n i . l a n g i s t u o a t a d l a i r e s ) i t a d r e s ( m a e r t s a t a d g n i m o c n i e h t f o n o i s r e v d e y a l e d e h t . ) p o k l c r e s ( t u o k c o l c l a i r e s f o e g d e g n i l l a f e h t n o d e t a d p u p o k l c r e s n o k l c r e s . f f i d l c e o5 1 4 1 t u o a t a d l a i r e s h t i w d e n g i l a e s a h p s i t a h t l a n g i s t u o k c o l c l a i r e s k c o l n e h w . h g i h s i ) t e d k c o l ( t c e t e d k c o l n e h w ) o t a d r e s ( k c o l c e c n e r e f e r h t i w s u o n o r h c n y s s i l a n g i s e h t , w o l s i t c e t e d . ) n / p n i k c f e r ( t u o k c f e rl t to 1 3. 1 e l b a t e e s . t u p t u o k c o l c e c n e r e f e r l t t d e d n e - e l g n i s e e v av 2 . 5 -C , 7 , 5 , 2 4 4 , 8 3 ) v 2 . 5 - ( r e w o p g o l a n a d n g ad n gC , 8 , 3 , 1 2 4 , 7 3 ) v 0 ( d n u o r g g o l a n a d n gd n gC , 7 1 , 6 1 , 9 , 2 2 , 9 1 , 9 2 , 7 2 5 3 , 0 3 d n u o r g v 2 . 5 -v 2 . 5 -C , 3 1 , 0 1 4 3 , 5 2 v 2 . 5 - v 5 +v 5 +C 8 2 , 8 1v 5 + c nCC2 1n o i t c e n n o c o n
5 S3014 sonet/sdh clock recovery and synthesis unit figure 4. 44 plcc pinout top view 0.152 ?005 0.050 ?002 0.649 ?005 0.692 ?005 0.029 ?003 0.172 ?005 0.620 ?010 top view 1 4 3 2 44 42 41 15 12 13 14 16 17 18 5 6 7 8 9 10 11 25 24 23 22 21 20 19 avee4* agnd2* serdatip serdatin refckinn agnd4* avee2* agnd * gnd gnd n/c serclkon gnd gnd tstclken -5.2v rst los refckout sel0 serdatop gnd serdaton sel1 sel2 gnd 26 27 28 31 34 33 32 30 29 39 38 37 36 35 40 43 avee * cap2 cap1 gnd +5v -5.2v +5v serclkop -5.2v lockdet * agnd1 * avee1 -5.2v gnd gnd refckinp avee3* agnd3* * analog power & gnd avee = -5.2v agnd = 0v all dimensions nominal in inches figure 5. 44 plcc package
6 S3014 sonet/sdh clock recovery and synthesis unit performance specifications parameter min typ max units condition nominal vco center frequency 622.08 mhz given refclk = serclk ? 4, 12 or serclk ? 32 per sel <2:0> settings clock synthesis output jitter oc-3/sts-3 oc-12/sts-12 .005 .015 .01 64 .03 48 ui(rms) ps (rms) ui(rms) ps (rms) in csu mode, given : ? 56ps rms jitter on refclk in 12 khz to 1 mhz band ? 14.1 ps rms jitter on refclk in 12 khz to 1 mhz band clock recovery output jitter .01 ui(rms) rms jitter, in lock reference clock frequency tolerance clock synthesis clock recovery -20 -100 20 100 ppm ppm required to meet sonet output frequency specification oc-3/sts-3 oc-12/sts-12 capture range lock range clock output duty cycle 45 200 +8,-12 55 ppm % % with respect to fixed reference frequency minimum transition density of 20% acquisition lock time oc-3/sts-3 oc-12/sts-12 64 16 m sec with device already powered up and valid refclk. reference clock input duty cycle 30 70 % of period reference clock rise & fall times 2.0 ns 10% to 90% of amplitude ecl output rise & fall times 850 ps 10% to 90%, 50 w to -2v equivalent load, 5 pf cap 1. these specs can be achieved with either a 51.84 mhz or a 155.52 mhz reference clock. 2. noise on refclk should be less than 14.1 ps rms in a jitter frequency band from 12 khz to 1 mhz. 3. specifications based on design values. not tested. 3 2,3 1 sel2 sel1 sel0 serclko refckout refckin 0 0 0 622.08 mhz 51.84 mhz 51.84 mhz 0 0 1 622.08 mhz 19.44 mhz 19.44 mhz 0 1 0 622.08 mhz 19.44 mhz 19.44 mhz 0 1 1 622.08 mhz 155.52 mhz 1 0 0 155.52 mhz 51.84 mhz 51.84 mhz 1 0 1 155.52 mhz 19.44 mhz 19.44 mhz table 1. mode select
7 S3014 sonet/sdh clock recovery and synthesis unit parameter min typ max unit ambient temperature under bias (industrial) -40 85 c ambient temperature under bias (commercial) 0 70 c junction temperature under bias -10 130 c voltage on vcc with respect to gnd 4.75 5.0 5.25 v voltage on vee with respect to gnd -4.2 -4.5/-5.2 -5.46 v voltage on any ttl input pin 0.0 vcc v voltage on any ecl input pin -2.0 0 v ttl/cmos output sink current 8 ma ttl/cmos output source current 1 ma ecl output source current (50 w to -2v) 14 25 ma supply current icc 10 17 ma iee 170 210 ma recommended operating conditions parameter min typ max unit case temperature under bias -55 125 c junction temperature under bias -55 150 c storage temperature -65 150 c voltage on vcc with respect to gnd -0.5 7.0 v voltage on vee with respect to gnd -8.0 0.5 v voltage on any ttl input pin -0.5 +5.5 v voltage on any ecl input pin -3.0 0.0 v ttl output sink current 20 ma ttl output source current 10 ma high speed ecl output source current 50 ma static discharge voltage 500 v absolute maximum ratings v ee (min) = -4.2v for ambient temperature 3 0?c, -4.5v for ambient temperature <0?c.
8 S3014 sonet/sdh clock recovery and synthesis unit ttl input/output dc characteristics 1 ecl input/output dc characteristics 3 1. these conditions will be met with an airflow of 400 lfpm. 2. these input levels provide a zeroCnoise immunity and should only be tested in a static, noise-free environment. symbol parameter test conditions min max unit v il 2 v ih 2 i il i ih i i i os v ik v ol v oh input low voltage input high voltage input low current input high current input high current at max vcc output short circuit current input clamp diode voltage ttl output low voltage ttl output high voltage guaranteed input low voltage for all inputs v cc = max, v in = 0.5v v cc = max, v in = 2.7v v cc = max, v in = 5.25v v cc = max, v out = 0.5v v cc = min, i in = -18.0ma v cc = min, i ol = 8ma v cc = min, i oh = -1.0ma 2.0 -400.0 -100.0 2.4 0.8 50.0 1.0 -25.0 0.5 volts volts ua ua ma ma volts volts -1.2 volts guaranteed input high voltage for all inputs (t a = -40 c to +85 c, v cc = 5 v 5%, v ee = -4.5 v 7% or -5.2 5%) symbol parameter test conditions min max unit signal name v il 1 input low voltage guaranteed input low voltage for all single ended inputs -2.00 -1.47 volts v ih 1 input high voltage guaranteed input high voltage for all single ended inputs -1.18 -0.80 volts v il 2 input low voltage guaranteed input low voltage for all differential inputs -2.00 -0.70 volts v ih 2 input high voltage guaranteed input high voltage for all differential inputs -1.75 -0.45 volts v ol output low voltage 50 w to -2v termination -2.00 -1.50 volts i il input low current v ee = max, v il = -1.95v -0.50 20.00 ua -1.0 20.00 ua los serdatip,serdatin, refclkp, refclkn i ih input high current v ee = max, v ih = -0.80v v ee = max, v diff = 0.5v -0.50 20.00 ua -1.0 20.00 ua los serdatip,serdatin, refclkp, refclkn v oh output high voltage 50 w to -2v termination -1.11 -0.62 volts v id 2,4 input diff voltage guaranteed input diff voltage for all differential inputs 0.25 1.40 volts v ee = max, v diff = 0.5v 1. single ended inputs 2. differential ecl inputs 3. these conditions will be met with an airflow of 400 lfpm. 4. when not used, tie the negative differential input to ground (ov), and tie the positive differential input to -2.0v. (t a = -40 c to +85 c, v cc = 5 v 5%, v ee = -4.5 v 7% or -5.2 5%)
9 S3014 sonet/sdh clock recovery and synthesis unit differential output to serdatip/n 330 w serclkop/n and serdatop/n output to ecl-compatible input ecl driver to refclk input 330 w 330 w vee 330 w 330 w vee optical to electrical ecl-compatible output to serdatip/n differential input 100 w ?v 0.1 m f external 100 w termination 50 w transmission line unbalanced ecl signal to serdatip/n differential input 330 w vee -2v 50 w 50 w 50 w transmission lines external 100 w termination external 100 w termination external 100 w termination S3014 S3014 S3014 S3014 S3014 figure 6. differential ecl input and output applications
10 S3014 sonet/sdh clock recovery and synthesis unit grade part package speed grade s-commercial/ 3014 a-44 plcc (com only) 1 C 155 mbit/s industrial d-44 plcc tep 6 C 622 mbit/s ordering information x xxxx x x C grade part number package speed grade amcc is a registered trademark of applied micro circuits corporation. copyright ? 1997 applied micro circuits corporation june 2, 1997 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (619) 450-9333 ? (800)755-2622 ? fax: (619) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1
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